1. Field of the Invention
The present invention relates to a semiconductor device and a layout method thereof, and more particularly to a semiconductor device equipped with mesh-pattern wirings, and a layout method thereof.
2. Description of Related Art
A typical semiconductor device includes a plurality of wiring layers. On each of the wiring layers, power-supply lines and signal lines are formed. For example, what is disclosed in Japanese Patent Application Laid-Open No. 2001-127162 is a structure in which a plurality of power-supply lines that extend in an X-direction are formed on a certain wiring layer, and a plurality of power-supply lines that extend in a Y-direction on another wiring layer, and the power-supply lines are connected through conductor plugs. In this manner, the power-supply lines are formed in a mesh pattern.
It is preferred that the electrical resistance of the power-supply lines that are formed in a mesh pattern be as low as possible. The reason is that, if the electrical resistance of the power-supply lines is high, a power-supply voltage that is supplied to circuit elements becomes lower due to a voltage drop. In recent years, an external power-supply voltage tends to be made lower. Therefore, it is very important to lower the resistance of the power-supply lines.
However, as microfabrication technology has advanced in recent years, the wiring width of the power-supply lines tends to be reduced. Accordingly, the electrical resistance of the power-supply lines formed in a mesh pattern tends to become higher. A technique for keeping the electrical resistance low is desired. Such demand is noticeable particularly in the field of power-supply lines. However, the same is true not only in the field of power-supply lines, but also in the field of other lines such as signal lines.